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HIPC
1999
Springer
13 years 12 months ago
Microcaches
We describe a radically new cache architecture and demonstrate that it offers a huge reduction in cache cost, size and power consumption whilst maintaining performance on a wide ra...
David May, Dan Page, James Irwin, Henk L. Muller
DATE
2003
IEEE
84views Hardware» more  DATE 2003»
14 years 28 days ago
PARLAK: Parametrized Lock Cache Generator
A system-on-chip lock cache (SoCLC) is an intellectual property (IP) core that provides effective lock synchronization in a heterogeneous multiprocessor shared-memory system-on-ac...
Bilge Saglam Akgul, Vincent John Mooney III
ISCA
1995
IEEE
120views Hardware» more  ISCA 1995»
13 years 11 months ago
Streamlining Data Cache Access with Fast Address Calculation
For many programs, especially integer codes, untolerated load instruction latencies account for a significant portion of total execution time. In this paper, we present the desig...
Todd M. Austin, Dionisios N. Pnevmatikatos, Gurind...
ICPP
2007
IEEE
14 years 1 months ago
Integrating Memory Compression and Decompression with Coherence Protocols in Distributed Shared Memory Multiprocessors
Ever-increasing memory footprint of applications and increasing mainstream popularity of shared memory parallel computing motivate us to explore memory compression potential in di...
Lakshmana Rao Vittanala, Mainak Chaudhuri
COCO
2003
Springer
102views Algorithms» more  COCO 2003»
14 years 26 days ago
Memoization and DPLL: Formula Caching Proof Systems
A fruitful connection between algorithm design and proof complexity is the formalization of the ¤¦¥¨§©§ approach to satisfiability testing in terms of tree-like resolution...
Paul Beame, Russell Impagliazzo, Toniann Pitassi, ...