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WWW
2005
ACM
14 years 8 months ago
Hierarchical substring caching for efficient content distribution to low-bandwidth clients
While overall bandwidth in the internet has grown rapidly over the last few years, and an increasing number of clients enjoy broadband connectivity, many others still access the i...
Utku Irmak, Torsten Suel
HPCA
2007
IEEE
14 years 8 months ago
LogTM-SE: Decoupling Hardware Transactional Memory from Caches
This paper proposes a hardware transactional memory (HTM) system called LogTM Signature Edition (LogTM-SE). LogTM-SE uses signatures to summarize a transaction's readand writ...
Luke Yen, Jayaram Bobba, Michael R. Marty, Kevin E...
GLVLSI
2011
IEEE
344views VLSI» more  GLVLSI 2011»
12 years 11 months ago
Circuit design of a dual-versioning L1 data cache for optimistic concurrency
This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...
Azam Seyedi, Adrià Armejach, Adrián ...
USENIX
2008
13 years 10 months ago
Prefetching with Adaptive Cache Culling for Striped Disk Arrays
Conventional prefetching schemes regard prediction accuracy as important because useless data prefetched by a faulty prediction may pollute the cache. If prefetching requires cons...
Sung Hoon Baek, Kyu Ho Park
HPCA
2011
IEEE
12 years 11 months ago
Archipelago: A polymorphic cache design for enabling robust near-threshold operation
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...