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DATE
1999
IEEE
147views Hardware» more  DATE 1999»
14 years 7 days ago
Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints
In this paper, a method for the automatic sizing of analog integrated circuits is presented. Basic sizing rules, representing circuit knowledge, are set up before the sizing and a...
Robert Schwencker, Josef Eckmueller, Helmut E. Gra...
ACSAC
2006
IEEE
14 years 2 months ago
Bluetooth Worms: Models, Dynamics, and Defense Implications
Recent occurrences of mobile worms like Cabir, Mabir and CommWarrior have created growing concerns over the security of data stored on mobile devices such as cell phones and PDAs....
Guanhua Yan, Stephan Eidenbenz
JMLR
2006
125views more  JMLR 2006»
13 years 7 months ago
Linear Programming Relaxations and Belief Propagation - An Empirical Study
The problem of finding the most probable (MAP) configuration in graphical models comes up in a wide range of applications. In a general graphical model this problem is NP hard, bu...
Chen Yanover, Talya Meltzer, Yair Weiss
PVLDB
2010
166views more  PVLDB 2010»
13 years 6 months ago
Complex Event Detection at Wire Speed with FPGAs
Complex event detection is an advanced form of data stream processing where the stream(s) are scrutinized to identify given event patterns. The challenge for many complex event pr...
Louis Woods, Jens Teubner, Gustavo Alonso
ASPDAC
2006
ACM
105views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Speed binning aware design methodology to improve profit under parameter variations
—Designing high-performance systems with high yield under parameter variations has raised serious design challenges in nanometer technologies. In this paper, we propose a profit-...
Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saib...