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TRIDENTCOM
2005
IEEE
15 years 11 months ago
Divide and Conquer: PC-Based Packet Trace Replay at OC-48 Speeds
Today’s Internet backbone networking devices need to be tested under realistic traffic conditions at transmission rates of OC-48 and above. While commercially available synthet...
Tao Ye, Darryl Veitch, Gianluca Iannaccone, Suprat...
157
Voted
ERSA
2003
118views Hardware» more  ERSA 2003»
15 years 7 months ago
A Novel Multi-Speed, Power Saving Architecture for SiGe HBT FPGA
The availability of SiGe HBT devices has opened a door for Gigahertz FPGAs. However, the large device power consumption limits its scale. In order to solve this problem, a Multipl...
Jong-Ru Guo, Chao You, Michael Chu, Kuan Zhou, You...
152
Voted
ISCAS
2007
IEEE
84views Hardware» more  ISCAS 2007»
15 years 12 months ago
High Speed 1-bit Bypass Adder Design for Low Precision Additions
—In this paper, we propose a high speed adder which is adopted for our reconfigurable architecture called FleXilicon. To support sub-word parallelism, the FleXilicon architecture...
Jong-Suk Lee, Dong Sam Ha
149
Voted
HIPEAC
2005
Springer
15 years 11 months ago
Enhancing Network Processor Simulation Speed with Statistical Input Sampling
Abstract. While cycle-accurate simulation tools have been widely used in modeling high-performance processors, such an approach can be hindered by the increasing complexity of the ...
Jia Yu, Jun Yang 0002, Shaojie Chen, Yan Luo, Laxm...
ICCV
2009
IEEE
16 years 10 months ago
Compact Signatures for High-Speed Interest Point Description and Matching
Prominent feature point descriptors such as SIFT and SURF allow reliable real-time matching but at a compu- tational cost that limits the number of points that can be handled on...
Michael Calonder, Vincent Lepetit, Pascal Fua, Kur...