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» Speeding up power estimation of embedded software
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DAC
2009
ACM
13 years 11 months ago
Reduction techniques for synchronous dataflow graphs
The Synchronous Dataflow (SDF) model of computation is popular for modelling the timing behaviour of real-time embedded hardware and software systems and applications. It is an es...
Marc Geilen
CORR
2010
Springer
113views Education» more  CORR 2010»
13 years 7 months ago
Multi-core: Adding a New Dimension to Computing
Invention of Transistors in 1948 started a new era in technology, called Solid State Electronics. Since then, sustaining development and advancement in electronics and fabrication ...
Md. Tanvir Al Amin
DATE
2005
IEEE
180views Hardware» more  DATE 2005»
14 years 29 days ago
A Coprocessor for Accelerating Visual Information Processing
Visual information processing will play an increasingly important role in future electronics systems. In many applications, e.g. video surveillance cameras, data throughput of mic...
Walter Stechele, L. Alvado Cárcel, Stephan ...
CSIE
2009
IEEE
13 years 11 months ago
An Efficient Mixed-Mode Execution Environment for C on Mobile Phone Platforms
Mobile devices are constrained in terms of computational power, battery lifetime and memory sizes. Software development for mobile devices is further complicated by application co...
Taekhoon Kim, Sungho Kim, Kirak Hong, Hwangho Kim,...
CODES
2009
IEEE
13 years 8 months ago
Efficient dynamic voltage/frequency scaling through algorithmic loop transformation
We present a novel loop transformation technique, particularly well suited for optimizing embedded compilers, where an increase in compilation time is acceptable in exchange for s...
Mohammad Ali Ghodrat, Tony Givargis