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» Stable models and difference logic
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DLT
2009
13 years 6 months ago
Branching-Time Temporal Logics with Minimal Model Quantifiers
Abstract. Temporal logics are a well investigated formalism for the specification and verification of reactive systems. Using formal verification techniques, we can ensure the corr...
Fabio Mogavero, Aniello Murano
CORR
2008
Springer
141views Education» more  CORR 2008»
13 years 8 months ago
Model checking memoryful linear-time logics over one-counter automata
We study complexity of the model-checking problems for LTL with registers (also known as freeze LTL and written LTL ) and for first-order logic with data equality tests (written F...
Stéphane Demri, Ranko Lazic, Arnaud Sangnie...
DEON
2010
Springer
13 years 9 months ago
Towards Metalogical Systematisation of Deontic Action Logics Based on Boolean Algebra
The aim of the present paper is to provide a metalogical systematisation in the area of deontic action logic based on Boolean algebra. Differences among the systems in question lie...
Robert Trypuz, Piotr Kulicki
ICCAD
1995
IEEE
134views Hardware» more  ICCAD 1995»
14 years 7 days ago
A delay model for logic synthesis of continuously-sized networks
ng certain electrical noise and power constraints.Abstract: We present a new delay model for use in logic synthesis. A traditional model treats the area of a library cell as consta...
Joel Grodstein, Eric Lehman, Heather Harkness, Bil...
GLVLSI
2003
IEEE
134views VLSI» more  GLVLSI 2003»
14 years 2 months ago
Modeling QCA for area minimization in logic synthesis
Concerned by the wall that Moore’s Law is expected to hit in the next decade, the integrated circuit community is turning to emerging nanotechnologies for continued device impro...
Nadine Gergel, Shana Craft, John Lach