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CC
2004
Springer
14 years 26 days ago
Using Multiple Memory Access Instructions for Reducing Code Size
An important issue in embedded systems design is the size of programs. As computing devices decrease in size, yet with more and more functions, better code size optimizations are i...
Neil Johnson, Alan Mycroft
ISPA
2004
Springer
14 years 25 days ago
Highly Reliable Linux HPC Clusters: Self-Awareness Approach
Abstract. Current solutions for fault-tolerance in HPC systems focus on dealing with the result of a failure. However, most are unable to handle runtime system configuration change...
Chokchai Leangsuksun, Tong Liu, Yudan Liu, Stephen...
MICRO
2003
IEEE
142views Hardware» more  MICRO 2003»
14 years 22 days ago
Hardware Support for Control Transfers in Code Caches
Many dynamic optimization and/or binary translation systems hold optimized/translated superblocks in a code cache. Conventional code caching systems suffer from overheads when con...
Ho-Seop Kim, James E. Smith
DATE
2010
IEEE
110views Hardware» more  DATE 2010»
14 years 17 days ago
An RDL-configurable 3D memory tier to replace on-chip SRAM
—In a conventional SoC designs, on-chip memories occupy more than the 50% of the total die area. 3D technology enables the distribution of logic and memories on separate stacked ...
Marco Facchini, Paul Marchal, Francky Catthoor, Wi...
DATE
2010
IEEE
162views Hardware» more  DATE 2010»
14 years 17 days ago
Error resilience of intra-die and inter-die communication with 3D spidergon STNoC
: Scaling down in very deep submicron (VDSM) technologies increases the delay, power consumption of on-chip interconnects, while the reliability and yield decrease. In high perform...
Vladimir Pasca, Lorena Anghel, Claudia Rusu, Ricca...