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EH
1999
IEEE
351views Hardware» more  EH 1999»
13 years 12 months ago
Evolvable Hardware or Learning Hardware? Induction of State Machines from Temporal Logic Constraints
Here we advocate an approach to learning hardware based on induction of finite state machines from temporal logic constraints. The method involves training on examples, constraint...
Marek A. Perkowski, Alan Mishchenko, Anatoli N. Ch...
ICST
2009
IEEE
14 years 2 months ago
Test Input Generation Using UML Sequence and State Machines Models
We propose a novel testing approach that combines information from UML sequence models and state machine models. Current approaches that rely solely on sequence models do not cons...
Aritra Bandyopadhyay, Sudipto Ghosh
SIGSOFT
2006
ACM
14 years 8 months ago
Scenarios, goals, and state machines: a win-win partnership for model synthesis
Models are increasingly recognized as an effective means for elaborating requirements and exploring designs. For complex systems, model building is far from an easy task. Efforts ...
Christophe Damas, Bernard Lambeau, Axel van Lamswe...
ICCAD
1999
IEEE
99views Hardware» more  ICCAD 1999»
13 years 12 months ago
FunState - an internal design representation for codesign
In this paper, an internal design model called FunState (functions driven by state machines) is presented that enables the representation of different types of system components a...
Lothar Thiele, Karsten Strehl, Dirk Ziegenbein, Ro...
HIPC
2004
Springer
14 years 1 months ago
A Parallel State Assignment Algorithm for Finite State Machines
This paper summarizes the design and implementation of a parallel algorithm for state assignment of large Finite State Machines (FSMs). High performance CAD tools are necessary to...
David A. Bader, Kamesh Madduri