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» State machine models of timing and circuit design
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ERSHOV
2003
Springer
14 years 26 days ago
Integration of Functional and Timed Testing of Real-Time and Concurrent Systems
The article presents an approach to model based testing of complex systems based on a generalization of finite state machines (FSM) and input output state machines (IOSM). The app...
Victor V. Kuliamin, Alexandre Petrenko, Nick V. Pa...
VALUETOOLS
2006
ACM
162views Hardware» more  VALUETOOLS 2006»
14 years 1 months ago
Using UML state machines and petri nets for the quantitative investigation of ETCS
This paper proposes the modeling of technical systems and their behavior by means of Unified Modeling Language (UML) State Machines and the extending UML Profile for Schedulabil...
Jan Trowitzsch, Armin Zimmermann
SIGSOFT
2006
ACM
14 years 8 months ago
Scenarios, goals, and state machines: a win-win partnership for model synthesis
Models are increasingly recognized as an effective means for elaborating requirements and exploring designs. For complex systems, model building is far from an easy task. Efforts ...
Christophe Damas, Bernard Lambeau, Axel van Lamswe...
ASPDAC
1995
ACM
130views Hardware» more  ASPDAC 1995»
13 years 11 months ago
Design for testability using register-transfer level partial scan selection
Abstract - An approach to top down design for testability using register-transfer level(RTL) partial scan selection is described. We propose a scan selection technique based on tes...
Akira Motohara, Sadami Takeoka, Toshinori Hosokawa...
IFIPTCS
2000
13 years 11 months ago
Hierarchical State Machines
Hierarchical state machines are finite state machines whose states themselves can be other machines. In spite of their popularity in many modeling tools for software design, very l...
Mihalis Yannakakis