1186 search results - page 14 / 238 » State machine models of timing and circuit design |
ICWE
2011
Springer
12 years 11 months ago
2011
Springer
Representational State Transfer (REST), as an architectural style for distributed hypermedia systems, enables scalable operation of the World Wide Web (WWW) and is the foundation f...
ICCAD
1999
IEEE
13 years 12 months ago
1999
IEEE
This paper presents a new method to synthesize timed asynchronous circuits directly from the specification without generating a state graph. The synthesis procedure begins with a ...
EVOW
2003
Springer
14 years 26 days ago
2003
Springer
Abstract. Many evolutionary algorithm applications involve either fitness functions with high time complexity or large dimensionality (hence very many fitness evaluations will typi...
ASYNC
2002
IEEE
14 years 19 days ago
2002
IEEE
Advanced clock-delayed1 and self-resetting domino circuits are becoming increasingly important design styles in aggressive synchronous as well as asynchronous design. Their design...
DFT
2007
IEEE
14 years 2 months ago
2007
IEEE
The paper discusses a novel approach for reduction of fault detection latency in a selfchecking sequential circuit. The Authors propose decomposing the finite state machine (FSM) ...