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» State machine models of timing and circuit design
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SIGMETRICS
2008
ACM
214views Hardware» more  SIGMETRICS 2008»
13 years 9 months ago
HMTT: a platform independent full-system memory trace monitoring system
Memory trace analysis is an important technology for architecture research, system software (i.e., OS, compiler) optimization, and application performance improvements. Many appro...
Yungang Bao, Mingyu Chen, Yuan Ruan, Li Liu, Jianp...
DATE
2008
IEEE
131views Hardware» more  DATE 2008»
14 years 3 months ago
Parametric Throughput Analysis of Synchronous Data Flow Graphs
Synchronous Data Flow Graphs (SDFGs) have proved to be a very successful tool for modeling, analysis and synthesis of multimedia applications targeted at both single- and multiproc...
Amir Hossein Ghamarian, Marc Geilen, Twan Basten, ...
HPCA
2006
IEEE
14 years 9 months ago
BulletProof: a defect-tolerant CMP switch architecture
As silicon technologies move into the nanometer regime, transistor reliability is expected to wane as devices become subject to extreme process variation, particle-induced transie...
Kypros Constantinides, Stephen Plaza, Jason A. Blo...
OSDI
2008
ACM
14 years 9 months ago
Improving MapReduce Performance in Heterogeneous Environments
MapReduce is emerging as an important programming model for large-scale data-parallel applications such as web indexing, data mining, and scientific simulation. Hadoop is an open-...
Matei Zaharia, Andy Konwinski, Anthony D. Joseph, ...
PADS
2006
ACM
14 years 2 months ago
Aurora: An Approach to High Throughput Parallel Simulation
A master/worker paradigm for executing large-scale parallel discrete event simulation programs over networkenabled computational resources is proposed and evaluated. In contrast t...
Alfred Park, Richard M. Fujimoto