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» State machine models of timing and circuit design
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DATE
2008
IEEE
168views Hardware» more  DATE 2008»
14 years 3 months ago
Cycle-approximate Retargetable Performance Estimation at the Transaction Level
This paper presents a novel cycle-approximate performance estimation technique for automatically generated transaction level models (TLMs) for heterogeneous multicore designs. The...
Yonghyun Hwang, Samar Abdi, Daniel Gajski
SSS
2010
Springer
125views Control Systems» more  SSS 2010»
13 years 6 months ago
Systematic Correct Construction of Self-stabilizing Systems: A Case Study
Design and implementation of distributed algorithms often involve many subtleties due to their complex structure, non-determinism, and low atomicity as well as occurrence of unanti...
Ananda Basu, Borzoo Bonakdarpour, Marius Bozga, Jo...
PVM
2010
Springer
13 years 7 months ago
Toward Performance Models of MPI Implementations for Understanding Application Scaling Issues
Abstract. Designing and tuning parallel applications with MPI, particularly at large scale, requires understanding the performance implications of different choices of algorithms ...
Torsten Hoefler, William Gropp, Rajeev Thakur, Jes...
SPAA
1995
ACM
14 years 16 days ago
Accounting for Memory Bank Contention and Delay in High-Bandwidth Multiprocessors
For years, the computation rate of processors has been much faster than the access rate of memory banks, and this divergence in speeds has been constantly increasing in recent yea...
Guy E. Blelloch, Phillip B. Gibbons, Yossi Matias,...
PLDI
2011
ACM
12 years 11 months ago
Caisson: a hardware description language for secure information flow
Information flow is an important security property that must be incorporated from the ground up, including at hardware design time, to provide a formal basis for a system’s roo...
Xun Li 0001, Mohit Tiwari, Jason Oberg, Vineeth Ka...