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» State machine models of timing and circuit design
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CODES
2009
IEEE
13 years 11 months ago
Cycle count accurate memory modeling in system level design
In this paper, we propose an effective automatic generation approach for a Cycle-Count Accurate Memory Model (CCAMM) from the Clocked Finite State Machine (CFSM) of the Cycle Accu...
Yi-Len Lo, Mao Lin Li, Ren-Song Tsay
FASE
2007
Springer
14 years 1 months ago
Activity-Driven Synthesis of State Machines
The synthesis of object behaviour from scenarios is a well-known and important issue in the transition from system analysis to system design. We describe a model transformation pro...
Rolf Hennicker, Alexander Knapp
INDIASE
2009
ACM
14 years 11 days ago
Automated review of natural language requirements documents: generating useful warnings with user-extensible glossaries driving
We present an approach to automating some of the quality assurance review of software requirements documents, and promoting best practices for requirements documentation. The syst...
Prateek Jain, Kunal Verma, Alex Kass, Reymonrod G....
DFT
2006
IEEE
122views VLSI» more  DFT 2006»
13 years 11 months ago
Efficient and Robust Delay-Insensitive QCA (Quantum-Dot Cellular Automata) Design
The concept of clocking for QCA, referred to as the four-phase clocking, is widely used. However, inherited characteristics of QCA, such as the way to hold state, the way to synch...
Minsu Choi, Myungsu Choi, Zachary D. Patitz, Nohpi...
ISCA
2006
IEEE
131views Hardware» more  ISCA 2006»
14 years 1 months ago
Reducing Startup Time in Co-Designed Virtual Machines
A Co-Designed Virtual Machine allows designers to implement a processor via a combination of hardware and software. Dynamic binary translation converts code written for a conventi...
Shiliang Hu, James E. Smith