1186 search results - page 27 / 238 » State machine models of timing and circuit design |
DSN
2002
IEEE
14 years 20 days ago
2002
IEEE
Designing applications with timeliness requirements in environments of uncertain synchrony is known to be a difficult problem. In this paper, we follow the perspective of timing ...
ASYNC
2004
IEEE
13 years 11 months ago
2004
IEEE
This paper presents a decomposition method for speedindependent circuit design that is capable of significantly reducing the cost of synthesis. In particular, this method synthesi...
TCAD
1998
13 years 7 months ago
1998
— Conventional methods for optimal sizing of wires and transistors use linear resistor-capacitor (RC) circuit models and the Elmore delay as a measure of signal delay. If the RC ...
ICCAD
2007
IEEE
14 years 4 months ago
2007
IEEE
— We introduce a remote activation scheme that aims to protect integrated circuits (IC) intellectual property (IP) against piracy. Remote activation enables designers to lock eac...
ITC
1998
IEEE
13 years 11 months ago
1998
IEEE
This paper presents a novel technique to evaluate the noncontrollability measures of state registers for partial scan design. Our model uses implicit techniques for finite state ma...