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» State machine models of timing and circuit design
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CC
2008
Springer
240views System Software» more  CC 2008»
13 years 9 months ago
Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs
JIT compilation is a model of execution which translates at run time critical parts of the program to a low level representation. Typically a JIT compiler produces machine code fro...
Etienne Bergeron, Marc Feeley, Jean-Pierre David
ISQED
2006
IEEE
155views Hardware» more  ISQED 2006»
14 years 1 months ago
FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs
This paper is concerned with statically analyzing the susceptibility of arbitrary combinational circuits to single event upsets that are becoming a significant concern for reliabi...
Bin Zhang, Wei-Shen Wang, Michael Orshansky
ICCAD
2008
IEEE
200views Hardware» more  ICCAD 2008»
13 years 1 months ago
Accurate Equivalent Energy Breakeven Time Estimation for Power Gating
Run-time Power Gating (RTPG) is a recent technique, which aims at aggressively reducing leakage power consumption. Energy breakeven time (EBT), or equivalent sleep time has been pr...
Hao Xu, Wen-Ben Jone, Ranga Vemuri
INFORMS
1998
142views more  INFORMS 1998»
13 years 7 months ago
Distributed State Space Generation of Discrete-State Stochastic Models
High-level formalisms such as stochastic Petri nets can be used to model complex systems. Analysis of logical and numerical properties of these models often requires the generatio...
Gianfranco Ciardo, Joshua Gluckman, David M. Nicol
TAMODIA
2007
13 years 8 months ago
From Task to Dialog Model in the UML
Many model-based approaches for user interface design start from a task model, for which the ConcurTaskTrees notation is frequently used. Despite this popularity and the importance...
Jan Van den Bergh, Karin Coninx