1186 search results - page 9 / 238 » State machine models of timing and circuit design |
ASPDAC
2001
ACM
13 years 11 months ago
2001
ACM
We propose a timing optimization technique for a complex finite state machine that consists of not only random logic but also data operators. In such a design, the timing critical...
ISMVL
2008
IEEE
14 years 2 months ago
2008
IEEE
Abstract—This paper presents fundamental logic structures designed using novel quantum dot gate FETs with three-state characteristics. This three-state FET manifests itself as a ...
DAC
1999
ACM
13 years 12 months ago
1999
ACM
We present a methodology for the watermarking of synchronous sequential circuits that makes it possible to identify the authorship of designs by imposing a digital watermark on th...
ATS
2005
IEEE
14 years 1 months ago
2005
IEEE
In this paper, we propose an oscillation-based test methodology for sequential testing. This approach provides many advantages over traditional methods. (1) It is at-speed testing...
DSRT
2005
IEEE
14 years 1 months ago
2005
IEEE
Timed automata provide useful state machine based representations for the validation and verification of realtime control systems. This paper introduces an algorithmic methodolog...