119 search results - page 12 / 24 » Static Energy Reduction Techniques for Microprocessor Caches |
ISCA
2006
IEEE
14 years 1 months ago
2006
IEEE
Level one cache normally resides on a processor’s critical path, which determines the clock frequency. Directmapped caches exhibit fast access time but poor hit rates compared w...
JCP
2007
13 years 7 months ago
2007
When the environmental conditions are stable, a typical Wireless Sensor Network (WSN) application may sense and process very similar or constant data values for long durations. Thi...
CGO
2005
IEEE
14 years 1 months ago
2005
IEEE
To minimize the surging power consumption of microprocessors, adaptive computing environments (ACEs) where microarchitectural resources can be dynamically tuned to match a program...
ICPP
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—As Chip-Multiprocessor systems (CMP) have become the predominant topology for leading microprocessors, critical components of the system are now integrated on a single c...
HPCA
2002
IEEE
14 years 8 months ago
2002
IEEE
This work is based on our philosophy of providing interlayer system-level power awareness in computing systems [26, 27]. Here, we couple this approach with our vision of multipart...