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» Static Energy Reduction Techniques for Microprocessor Caches
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CASES
2007
ACM
14 years 23 days ago
Cache leakage control mechanism for hard real-time systems
Leakage energy consumption is an increasingly important issue as the technology continues to shrink. Since on-chip caches constitute a major portion of the processor's transi...
Jaw-Wei Chi, Chia-Lin Yang, Yi-Jung Chen, Jian-Jia...
EUROPAR
2010
Springer
13 years 9 months ago
Power-Efficient Spilling Techniques for Chip Multiprocessors
Abstract. Current trends in CMPs indicate that the core count will increase in the near future. One of the main performance limiters of these forthcoming microarchitectures is the ...
Enric Herrero, José González, Ramon ...
ASPLOS
2008
ACM
13 years 10 months ago
Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessors
Integrating more processor cores on-die has become the unanimous trend in the microprocessor industry. Most of the current research thrusts using chip multiprocessors (CMPs) as th...
Chinnakrishnan S. Ballapuram, Ahmad Sharif, Hsien-...
ICS
2009
Tsinghua U.
14 years 1 months ago
Dynamic task set partitioning based on balancing memory requirements to reduce power consumption
ABSTRACT Because of technology advances power consumption has emerged up as an important design issue in modern high-performance microprocessors. As a consequence, research on redu...
Diana Bautista, Julio Sahuquillo, Houcine Hassan, ...
LCTRTS
2007
Springer
14 years 2 months ago
Compiler-managed partitioned data caches for low power
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...
Rajiv A. Ravindran, Michael L. Chu, Scott A. Mahlk...