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» Static Energy Reduction Techniques for Microprocessor Caches
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MICRO
2009
IEEE
178views Hardware» more  MICRO 2009»
14 years 2 months ago
Improving cache lifetime reliability at ultra-low voltages
Voltage scaling is one of the most effective mechanisms to reduce microprocessor power consumption. However, the increased severity of manufacturing-induced parameter variations a...
Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerso...
RTSS
2005
IEEE
14 years 1 months ago
A Hybrid Static/Dynamic DVS Scheduling for Real-Time Systems with (m, k)-Guarantee
Energy reduction is critical to increase the mobility and to extend the mission period in the development of today’s pervasive computing systems. On the other hand, however, ene...
Linwei Niu, Gang Quan
IPCCC
2006
IEEE
14 years 1 months ago
OS-aware tuning: improving instruction cache energy efficiency on system workloads
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...
Tao Li, Lizy K. John
ISLPED
2010
ACM
202views Hardware» more  ISLPED 2010»
13 years 7 months ago
MODEST: a model for energy estimation under spatio-temporal variability
Estimation of static and dynamic energy of caches is critical for high-performance low-power designs. Commercial CAD tools performing energy estimation statically are not aware of...
Shrikanth Ganapathy, Ramon Canal, Antonio Gonz&aac...
ICCAD
2003
IEEE
152views Hardware» more  ICCAD 2003»
14 years 4 months ago
Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches
On-chip L1 and L2 caches represent a sizeable fraction of the total power consumption of microprocessors. In deep sub-micron technology, the subthreshold leakage power is becoming...
Nam Sung Kim, David Blaauw, Trevor N. Mudge