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SBACPAD
2004
IEEE
86views Hardware» more  SBACPAD 2004»
13 years 8 months ago
Multi-Profile Instruction Based Compression
Code compression has been used to minimize the memory area requirement of embedded systems. Recently, performance improvement and energy consumption reductionare observed as a by-...
Eduardo Wanderley Netto, Rodolfo Azevedo, Paulo Ce...
ISCA
2000
IEEE
99views Hardware» more  ISCA 2000»
13 years 12 months ago
Transient fault detection via simultaneous multithreading
Smaller feature sizes, reduced voltage levels, higher transistor counts, and reduced noise margins make future generations of microprocessors increasingly prone to transient hardw...
Steven K. Reinhardt, Shubhendu S. Mukherjee
PLDI
2005
ACM
14 years 1 months ago
Automatic pool allocation: improving performance by controlling data structure layout in the heap
This paper describes Automatic Pool Allocation, a transformation framework that segregates distinct instances of heap-based data structures into seperate memory pools and allows h...
Chris Lattner, Vikram S. Adve
ECRTS
2007
IEEE
14 years 1 months ago
WCET-Directed Dynamic Scratchpad Memory Allocation of Data
Many embedded systems feature processors coupled with a small and fast scratchpad memory. To the difference with caches, allocation of data to scratchpad memory must be handled by...
Jean-François Deverge, Isabelle Puaut
CODES
2007
IEEE
14 years 1 months ago
HW/SW co-design for Esterel processing
We present a co-synthesis approach that accelerates reactive software processing by moving the calculation of complex expressions into external combinational hardware. The startin...
Sascha Gädtke, Claus Traulsen, Reinhard von H...