Sciweavers

328 search results - page 33 / 66
» Static performance prediction of skeletal parallel programs
Sort
View
CASES
2006
ACM
14 years 7 days ago
Power efficient branch prediction through early identification of branch addresses
Ever increasing performance requirements have elevated deeply pipelined architectures to a standard even in the embedded processor domain, requiring the incorporation of dynamic b...
Chengmo Yang, Alex Orailoglu
OSDI
2008
ACM
14 years 8 months ago
Gadara: Dynamic Deadlock Avoidance for Multithreaded Programs
Deadlock is an increasingly pressing concern as the multicore revolution forces parallel programming upon the average programmer. Existing approaches to deadlock impose onerous bu...
Manjunath Kudlur, Scott A. Mahlke, Stéphane...
ISCA
2003
IEEE
88views Hardware» more  ISCA 2003»
14 years 1 months ago
Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors
Clustered microarchitectures are an attractive alternative to large monolithic superscalar designs due to their potential for higher clock rates in the face of increasingly wire-d...
Rajeev Balasubramonian, Sandhya Dwarkadas, David H...
ISSS
2002
IEEE
124views Hardware» more  ISSS 2002»
14 years 1 months ago
Timing Analysis of Embedded Software for Speculative Processors
Static timing analysis of embedded software is important for systems with hard real-time constraints. To accurately estimate time bounds, it is essential to model the underlying m...
Abhik Roychoudhury, Xianfeng Li, Tulika Mitra
ASPLOS
2012
ACM
12 years 4 months ago
Chameleon: operating system support for dynamic processors
The rise of multi-core processors has shifted performance efforts towards parallel programs. However, single-threaded code, whether from legacy programs or ones difficult to para...
Sankaralingam Panneerselvam, Michael M. Swift