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DAC
2005
ACM
13 years 9 months ago
Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions
Variability of process parameters makes prediction of digital circuit timing characteristics an important and challenging problem in modern chip design. Recently, statistical stat...
Hongliang Chang, Vladimir Zolotov, Sambasivan Nara...
GLVLSI
2008
IEEE
147views VLSI» more  GLVLSI 2008»
14 years 1 months ago
Statistical timing analysis of flip-flops considering codependent setup and hold times
Statistical static timing analysis (SSTA) plays a key role in determining performance of the VLSI circuits implemented in state-of-the-art CMOS technology. A pre-requisite for emp...
Safar Hatami, Hamed Abrishami, Massoud Pedram
ICCAD
2005
IEEE
176views Hardware» more  ICCAD 2005»
14 years 4 months ago
Statistical gate sizing for timing yield optimization
— Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely...
Debjit Sinha, Narendra V. Shenoy, Hai Zhou
SERP
2004
13 years 8 months ago
Run-Time Cohesion Metrics: An Empirical Investigation
Cohesion is one of the fundamental measures of the 'goodness' of a software design. The most accepted and widely studied object-oriented cohesion metric is Chidamber and...
Áine Mitchell, James F. Power
TVLSI
2008
105views more  TVLSI 2008»
13 years 7 months ago
Fast Estimation of Timing Yield Bounds for Process Variations
With aggressive scaling down of feature sizes in VLSI fabrication, process variation has become a critical issue in designs. We show that two necessary conditions for the "Max...
Ruiming Chen, Hai Zhou