262 search results - page 18 / 53 » Static timing analysis for modeling QoS in networks-on-chip |
ICCAD
2005
IEEE
14 years 4 months ago
2005
IEEE
— As technology scales into the sub-90nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as sta...
FUIN
2007
13 years 7 months ago
2007
The paper presents a method of abstraction for timed systems. To extract an abstract model of a timed system we propose to use static analysis, namely a technique called path compr...
CODES
2008
IEEE
14 years 2 months ago
2008
IEEE
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the p...
CODES
2008
IEEE
14 years 2 months ago
2008
IEEE
Application-specific system-on-chip platforms create the opportunity to customize the cache configuration for optimal performance with minimal chip estate. Simulation, in partic...
ISSS
2002
IEEE
14 years 17 days ago
2002
IEEE
Static timing analysis of embedded software is important for systems with hard real-time constraints. To accurately estimate time bounds, it is essential to model the underlying m...