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» Static timing analysis for modeling QoS in networks-on-chip
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RTCSA
1999
IEEE
13 years 12 months ago
Schedulability-Driven Communication Synthesis for Time Triggered Embedded Systems
Abstract. We present an approach to static priority preemptive process scheduling for the synthesis of hard realtime distributed embedded systems where communication plays an impor...
Paul Pop, Petru Eles, Zebo Peng
VLSID
2004
IEEE
147views VLSI» more  VLSID 2004»
14 years 8 months ago
Computing Silent Gate Models for Noise Analysis from Slew and Delay Tables
Abstract--In this paper, we present a new approach to calculate the steady state resistance values for CMOS library gates. These resistances are defined as simple equivalent models...
Shabbir H. Batterywala, Narendra V. Shenoy
RTSS
2003
IEEE
14 years 27 days ago
Data Caches in Multitasking Hard Real-Time Systems
Data caches are essential in modern processors, bridging the widening gap between main memory and processor speeds. However, they yield very complex performance models, which make...
Xavier Vera, Björn Lisper, Jingling Xue
RTAS
2005
IEEE
14 years 1 months ago
Timing Analysis of TCP Servers for Surviving Denial-of-Service Attacks
— Denial-of-service attacks are becoming more frequent and sophisticated. Researchers have proposed a variety of defenses, including better system configurations, infrastructure...
V. Krishna Nandivada, Jens Palsberg
ICSM
2002
IEEE
14 years 17 days ago
STA - A Conceptual Model for System Evolution
A great deal of work on software maintenance focuses on source code analysis and manipulation. Code is viewed as a static entity that is – more or less – separated from the sy...
Markus Pizka