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» Static timing analysis for modeling QoS in networks-on-chip
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DATE
2007
IEEE
128views Hardware» more  DATE 2007»
14 years 1 months ago
Accounting for cache-related preemption delay in dynamic priority schedulability analysis
Recently there has been considerable interest in incorporating timing effects of microarchitectural features of processors (e.g. caches and pipelines) into the schedulability anal...
Lei Ju, Samarjit Chakraborty, Abhik Roychoudhury
CORR
2011
Springer
142views Education» more  CORR 2011»
12 years 11 months ago
Taming Numbers and Durations in the Model Checking Integrated Planning System
The Model Checking Integrated Planning System (MIPS) has shown distinguished performance in the second and third international planning competitions. With its object-oriented fram...
Stefan Edelkamp
BMCBI
2008
115views more  BMCBI 2008»
13 years 7 months ago
Principal components analysis based methodology to identify differentially expressed genes in time-course microarray data
Background: Time-course microarray experiments are being increasingly used to characterize dynamic biological processes. In these experiments, the goal is to identify genes differ...
Sudhakar Jonnalagadda, Rajagopalan Srinivasan
WINET
2010
91views more  WINET 2010»
13 years 6 months ago
Route duration modeling for mobile ad-hoc networks
In this paper, we present a model that estimates the time duration of routes formed by several intermediate nodes in mobile multi-hop ad-hoc networks. First, we analyze a 3-node ro...
Michael Pascoe-Chalke, Javier Gomez, Victor Rangel...
GLVLSI
2010
IEEE
190views VLSI» more  GLVLSI 2010»
13 years 9 months ago
A linear statistical analysis for full-chip leakage power with spatial correlation
In this paper, we present an approved linear-time algorithm for statistical leakage analysis in the present of any spatial correlation condition (strong or weak). The new algorith...
Ruijing Shen, Sheldon X.-D. Tan, Jinjun Xiong