262 search results - page 39 / 53 » Static timing analysis for modeling QoS in networks-on-chip |
ITC
2003
IEEE
14 years 26 days ago
2003
IEEE
A technique to derive test vectors that exercise the worstcase delay effects in a domino circuit in the presence of crosstalk is described. A model for characterizing the delay of...
ICCV
2011
IEEE
12 years 7 months ago
2011
IEEE
Background modelling on tensor field has recently been proposed for foreground detection tasks. Taking into account the Riemannian structure of the tensor manifold, recent resear...
DATE
2011
IEEE
12 years 11 months ago
2011
IEEE
Current processors are optimized for average case performance, often leading to a high worst-case execution time (WCET). Many architectural features that increase the average case...
ICST
2009
IEEE
14 years 2 months ago
2009
IEEE
GEGICK, MICHAEL CHARLES. Predicting Attack-prone Components with Source Code Static Analyzers. (Under the direction of Laurie Williams). No single vulnerability detection techniqu...
CSFW
2009
IEEE
14 years 2 months ago
2009
IEEE
Timeout mechanisms are a useful feature for web applications. However, these mechanisms need to be used with care because, if used as-is, they are vulnerable to timing attacks. Th...