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FPGA
1999
ACM
174views FPGA» more  FPGA 1999»
14 years 1 days ago
Reduction of Latency and Resource Usage in Bit-Level Pipelined Data Paths for FPGAs
Pipelining of data path structures increases the throughput rate at the expense of enlarged resource usage and latency unless architectures optimized towards specific applications...
Peter Kollig, Bashir M. Al-Hashimi
ISCAPDCS
2001
13 years 9 months ago
End-user Tools for Application Performance Analysis Using Hardware Counters
One purpose of the end-user tools described in this paper is to give users a graphical representation of performance information that has been gathered by instrumenting an applica...
Kevin S. London, Jack Dongarra, Shirley Moore, Phi...
VTS
2006
IEEE
93views Hardware» more  VTS 2006»
14 years 1 months ago
Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring
A new algorithm for identifying stuck faults in combinational circuits that cannot be detected by a given input sequence is presented. Other than pre and post-processing steps, ce...
Vishwani D. Agrawal, Soumitra Bose, Vijay Gangaram
ANCS
2009
ACM
13 years 5 months ago
Design and performance analysis of a DRAM-based statistics counter array architecture
The problem of maintaining efficiently a large number (say millions) of statistics counters that need to be updated at very high speeds (e.g. 40 Gb/s) has received considerable re...
Haiquan (Chuck) Zhao, Hao Wang, Bill Lin, Jun (Jim...
ISCC
2008
IEEE
148views Communications» more  ISCC 2008»
14 years 2 months ago
Data collection in sensor networks with data mules: An integrated simulation analysis
Wireless sensor networks (WSNs) have emerged as the enabling technology for a wide range of applications. In the context of environmental monitoring, especially in urban scenarios...
Giuseppe Anastasi, Marco Conti, Mario Di Francesco