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» Statistical Delay Modeling in Logic Design and Synthesis
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ISPD
2003
ACM
110views Hardware» more  ISPD 2003»
14 years 1 months ago
Explicit gate delay model for timing evaluation
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
Muzhou Shao, Martin D. F. Wong, Huijing Cao, Youxi...
DATE
2010
IEEE
175views Hardware» more  DATE 2010»
14 years 12 days ago
Approximate logic synthesis for error tolerant applications
─ Error tolerance formally captures the notion that – for a wide variety of applications including audio, video, graphics, and wireless communications – a defective chip that...
Doochul Shin, Sandeep K. Gupta
EUROMICRO
1999
IEEE
14 years 22 days ago
Design Space Exploration in System Level Synthesis under Memory Constraints
This paper addresses the problem of component selection, task assignment and task scheduling for distributed embedded computer systems. Such systems have a large number of constra...
Radoslaw Szymanek, Krzysztof Kuchcinski
SPEECH
2010
142views more  SPEECH 2010»
13 years 6 months ago
Analysis of statistical parametric and unit selection speech synthesis systems applied to emotional speech
We have applied two state-of-the-art speech synthesis techniques (unit selection and HMM-based synthesis) to the synthesis of emotional speech. A series of carefully designed perc...
Roberto Barra-Chicote, Junichi Yamagishi, Simon Ki...
INTEGRATION
2008
87views more  INTEGRATION 2008»
13 years 8 months ago
SafeResynth: A new technique for physical synthesis
Physical synthesis is a relatively young field in Electronic Design Automation. Many published optimizations for physical synthesis end up hurting the quality of the final design,...
Kai-Hui Chang, Igor L. Markov, Valeria Bertacco