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DFT
2007
IEEE
104views VLSI» more  DFT 2007»
14 years 2 months ago
Reduction of Fault Latency in Sequential Circuits by using Decomposition
The paper discusses a novel approach for reduction of fault detection latency in a selfchecking sequential circuit. The Authors propose decomposing the finite state machine (FSM) ...
Ilya Levin, Benjamin Abramov, Vladimir Ostrovsky
DATE
1999
IEEE
144views Hardware» more  DATE 1999»
13 years 12 months ago
A Method to Diagnose Faults in Linear Analog Circuits using an Adaptive Tester
This work presents a new diagnosis method for use in an adaptive analog tester. The tester is able to detect faults in any linear circuit by learning a reference behavior in a fir...
Érika F. Cota, Luigi Carro, Marcelo Lubasze...
PRDC
1999
IEEE
13 years 12 months ago
Experimental Assessment of COTS DBMS Robustness under Transient Faults
This paper evaluates the behavior of a common off-theshelf (COTS) database management system (DBMS) in presence of transient faults. Database applications have traditionally been ...
Diamantino Costa, Henrique Madeira
QEST
2007
IEEE
14 years 1 months ago
Probabilistic Model-Checking Support for FMEA
Failure Mode and Effect Analysis (FMEA) is a method for assessing cause-consequence relations between component faults and hazards that may occur during the lifetime of a system. ...
Lars Grunske, Robert Colvin, Kirsten Winter
ICCD
2008
IEEE
202views Hardware» more  ICCD 2008»
14 years 4 months ago
CrashTest: A fast high-fidelity FPGA-based resiliency analysis framework
— Extreme scaling practices in silicon technology are quickly leading to integrated circuit components with limited reliability, where phenomena such as early-transistor failures...
Andrea Pellegrini, Kypros Constantinides, Dan Zhan...