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FPGA
2005
ACM
105views FPGA» more  FPGA 2005»
14 years 1 months ago
Soft error rate estimation and mitigation for SRAM-based FPGAs
FPGA-based designs are more susceptible to single-event upsets (SEUs) compared to ASIC designs. Soft error rate (SER) estimation is a crucial step in the design of soft error tole...
Ghazanfar Asadi, Mehdi Baradaran Tahoori
WISES
2004
13 years 9 months ago
Embedded Real-Time-Tracer - An Approach with IDE
-- Debugging software that runs on highly integrated System-on-Chip devices is complicated because conventional debug tools (like traditional In-Circuit Emulators and Logic Analyze...
Babak Rahbaran, Matthias Függer, Andreas Stei...
VTS
2003
IEEE
89views Hardware» more  VTS 2003»
14 years 28 days ago
Diagnosis of Delay Defects Using Statistical Timing Models
— In this paper, we study the problem of delay defect diagnosis based on statistical timing models. We propose a diagnosis algorithm that can effectively utilize statistical timi...
Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-...
CACM
2008
131views more  CACM 2008»
13 years 7 months ago
Exterminator: Automatically correcting memory errors with high probability
Programs written in C and C++ are susceptible to memory errors, including buffer overflows and dangling pointers. These errors, which can lead to crashes, erroneous execution, and...
Gene Novark, Emery D. Berger, Benjamin G. Zorn
FDTC
2006
Springer
74views Cryptology» more  FDTC 2006»
13 years 11 months ago
Fault Attack Resistant Cryptographic Hardware with Uniform Error Detection
Traditional hardware error detection methods based on linear codes make assumptions about the typical or expected errors and faults and concentrate the detection power towards the ...
Konrad J. Kulikowski, Mark G. Karpovsky, Alexander...