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    » Statistical gate sizing for timing yield optimization
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    ICCAD
    2006
    IEEE
    141views Hardware» more  ICCAD 2006»
    Algorithms for MIS vector generation and pruning
    14 years 4 months ago
    Algorithms for MIS vector generation and pruning
    Download  www.ece.utah.edu
    Ignoring the effect of simultaneous switching for logic gates causes silicon failures for high performance microprocessor designs. The main reason to omit this effect is the run...
    Kenneth S. Stevens, Florentin Dartu
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    TCAD
    2010
    164views more  TCAD 2010»
    Advanced Variance Reduction and Sampling Techniques for Efficient Statistical Timing Analysis
    13 years 2 months ago
    Advanced Variance Reduction and Sampling Techniques for Efficient Statistical Timing Analysis
    Download  www.vlsi.uwaterloo.ca
    The Monte-Carlo (MC) technique is a traditional solution for a reliable statistical analysis, and in contrast to probabilistic methods, it can account for any complicate model. How...
    Javid Jaffari, Mohab Anis
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    DAC
    1999
    ACM
    179views Computer Architecture» more  DAC 1999»
    A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design
    14 years 8 months ago
    A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design
    Download  www-ise2.ist.osaka-u.ac.jp
    We propose a method for power optimization that considers glitch reduction by gate sizing based on the statistical estimation of glitch transitions. Our method reduces not only th...
    Masanori Hashimoto, Hidetoshi Onodera, Keikichi Ta...
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    DATE
    2010
    IEEE
    134views Hardware» more  DATE 2010»
    Combining optimizations in automated low power design
    13 years 6 months ago
    Combining optimizations in automated low power design
    Download  www.doc.ic.ac.uk
    —Starting from sequential programs, we present an approach combining data reuse, multi-level MapReduce, and pipelining to automatically find the most power-efficient designs th...
    Qiang Liu, Tim Todman, Wayne Luk
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    IOR
    2008
    109views more  IOR 2008»
    Polynomial-Time Algorithms for Stochastic Uncapacitated Lot-Sizing Problems
    13 years 7 months ago
    Polynomial-Time Algorithms for Stochastic Uncapacitated Lot-Sizing Problems
    Download  www.ise.ufl.edu
    In 1958, Wagner and Whitin published a seminal paper on the deterministic uncapacitated lot-sizing problem, a fundamental model that is embedded in many practical production plann...
    Yongpei Guan, Andrew J. Miller
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