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ICCAD
2003
IEEE
127views Hardware» more  ICCAD 2003»
14 years 7 months ago
Code Placement with Selective Cache Activity Minimization for Embedded Real-time Software Design
– Many embedded system designs usually impose (hard) read-time constraints on tasks. Thus, computing a tight upper bound of the worst case execution time (WCET) of a software is ...
Junhyung Um, Taewhan Kim
HPCA
2004
IEEE
14 years 10 months ago
Reducing the Scheduling Critical Cycle Using Wakeup Prediction
For highest performance, a modern microprocessor must be able to determine if an instruction is ready in the same cycle in which it is to be selected for execution. This creates a...
Todd E. Ehrhart, Sanjay J. Patel
ICCS
2007
Springer
14 years 4 months ago
Cyberinfrastructure for Contamination Source Characterization in Water Distribution Systems
This paper describes a preliminary cyberinfrastructure for contaminant characterization in water distribution systems and its deployment on the grid. The cyberinfrastructure consis...
Sarat Sreepathi, Kumar Mahinthakumar, Emily M. Zec...
DATE
2006
IEEE
125views Hardware» more  DATE 2006»
14 years 4 months ago
Design and implementation of a rendering algorithm in a SIMD reconfigurable architecture (MorphoSys)
In this paper we analyze a 3D image rendering algorithm and the different mapping schemes to implement it in a SIMD reconfigurable architecture. 3D image render is highly computat...
Javier Davila, Alfonso de Torres, Jose Manuel Sanc...
CF
2010
ACM
14 years 3 months ago
Load balancing using dynamic cache allocation
Supercomputers need a huge budget to be built and maintained. To maximize the usage of their resources, application developers spend time to optimize the code of the parallel appl...
Miquel Moretó, Francisco J. Cazorla, Rizos ...