1534 search results - page 265 / 307 » Stochastic Bounds on Execution Times of Parallel Computation... |
DAC
2005
ACM
13 years 9 months ago
2005
ACM
In this paper we present the impact of dynamically translating any sequence of instructions into combinational logic. The proposed approach combines a reconfigurable architecture ...
IPPS
2009
IEEE
14 years 2 months ago
2009
IEEE
— There are many grid-based applications where a timely response to an important event is needed. Often such response can require a significant computation and possibly communic...
ISORC
2002
IEEE
14 years 19 days ago
2002
IEEE
Object-oriented, concurrent, and event-based programming models provide a natural framework in which to express the behavior of distributed and embedded software systems. However,...
CODES
2005
IEEE
14 years 1 months ago
2005
IEEE
We present a new scheme for dynamic voltage and frequency scaling (DVS) for processing multimedia streams on architectures with restricted buffer sizes. The main advantage of our ...
CODES
2008
IEEE
14 years 2 months ago
2008
IEEE
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the p...