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» Storage coding for wear leveling in flash memories
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EH
2005
IEEE
119views Hardware» more  EH 2005»
14 years 1 months ago
Survivability of Embryonic Memories: Analysis and Design Principles
This paper proposes an original approach to the reliability analysis for Embryonics [4], by introducing the accuracy threshold measure, borrowed from fault-tolerant quantum comput...
Lucian Prodan, Mihai Udrescu, Mircea Vladutiu
ICCD
2006
IEEE
138views Hardware» more  ICCD 2006»
14 years 4 months ago
Delay and Area Efficient First-level Cache Soft Error Detection and Correction
—Soft error rates are an increasing problem in modern VLSI circuits. Commonly used error correcting codes reduce soft error rates in large memories and second level caches but ar...
Karl Mohr, Lawrence Clark
CLUSTER
2008
IEEE
14 years 2 months ago
Active storage using object-based devices
—The increasing performance and decreasing cost of processors and memory are causing system intelligence to move from the CPU to peripherals such as disk drives. Storage system d...
Tina Miriam John, Anuradharthi Thiruvenkata Ramani...
HPCA
2012
IEEE
12 years 3 months ago
Improving write operations in MLC phase change memory
Phase change memory (PCM) recently has emerged as a promising technology to meet the fast growing demand for large capacity memory in modern computer systems. In particular, multi...
Lei Jiang, Bo Zhao, Youtao Zhang, Jun Yang 0002, B...
ASAP
2003
IEEE
133views Hardware» more  ASAP 2003»
14 years 25 days ago
Storage Management in Process Networks using the Lexicographically Maximal Preimage
At the Leiden Embedded Research Center, we are developing a compiler called Compaan that automatically translates signal processing applications written in Matlab into Kahn Proces...
Alexandru Turjan, Bart Kienhuis