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» Strategies for Branch Target Buffers
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MICRO
1991
IEEE
93views Hardware» more  MICRO 1991»
14 years 2 months ago
Strategies for Branch Target Buffers
Brian K. Bray, Michael J. Flynn
ICCD
2002
IEEE
132views Hardware» more  ICCD 2002»
14 years 8 months ago
Applying Decay Strategies to Branch Predictors for Leakage Energy Savings
With technology advancing toward deep submicron, leakage energy is of increasing concern, especially for large onchip array structures such as caches and branch predictors. Recent...
Zhigang Hu, Philo Juang, Kevin Skadron, Douglas W....
ISPASS
2009
IEEE
14 years 6 months ago
Experiment flows and microbenchmarks for reverse engineering of branch predictor structures
Insights into branch predictor organization and operation can be used in architecture-aware compiler optimizations to improve program performance. Unfortunately, such details are ...
Vladimir Uzelac, Aleksandar Milenkovic
RTCSA
2009
IEEE
14 years 5 months ago
Branch Target Buffers: WCET Analysis Framework and Timing Predictability
—One step in the verification of hard real-time systems is to determine upper bounds on the worst-case execution times (WCET) of tasks. To obtain tight bounds, a WCET analysis h...
Daniel Grund, Jan Reineke, Gernot Gebhard
FDTC
2007
Springer
124views Cryptology» more  FDTC 2007»
14 years 5 months ago
Countermeasures against Branch Target Buffer Attacks
Branch Prediction Analysis has been recently proposed as an attack method to extract the key from software implementations of the RSA public key cryptographic algorithm. In this p...
Giovanni Agosta, Luca Breveglieri, Gerardo Pelosi,...