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PLDI
2012
ACM
11 years 10 months ago
Dynamic synthesis for relaxed memory models
Modern architectures implement relaxed memory models which may reorder memory operations or execute them non-atomically. Special instructions called memory fences are provided, al...
Feng Liu, Nayden Nedev, Nedyalko Prisadnikov, Mart...
ASPLOS
2000
ACM
14 years 11 hour ago
Power Aware Page Allocation
One of the major challenges of post-PC computing is the need to reduce energy consumption, thereby extending the lifetime of the batteries that power these mobile devices. Memory ...
Alvin R. Lebeck, Xiaobo Fan, Heng Zeng, Carla Schl...
IPPS
2006
IEEE
14 years 1 months ago
A simulator for parallel applications with dynamically varying compute node allocation
Dynamically allocating computing nodes to parallel applications is a promising technique for improving the utilization of cluster resources. We introduce the concept of dynamic ef...
Basile Schaeli, B. Gerlach, Roger D. Hersch
JSA
2007
162views more  JSA 2007»
13 years 7 months ago
Exploration of distributed shared memory architectures for NoC-based multiprocessors
Multiprocessor system-on-chip (MP-SoC) platforms represent an emerging trend for embedded multimedia applications. To enable MP-SoC platforms, scalable communication-centric inter...
Matteo Monchiero, Gianluca Palermo, Cristina Silva...
ISQED
2006
IEEE
106views Hardware» more  ISQED 2006»
14 years 1 months ago
Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration
We propose an accurate architecture-level power estimation method for SRAM memories. This hybrid method is composed of an analytical part for dynamic power estimation and a circui...
Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-...