Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration

We propose an accurate architecture-level power estimation method for SRAM memories. This hybrid method is composed of an analytical part for dynamic power estimation and a circuit-simulation backend used to obtain static leakage power values of all basic memory components. The method is flexible in that memory size is an arbitrary parameter. In a comparison to circuit-level simulations (Hspice) of complete 2 KBytes and 8 KBytes 6T-SRAM memories implemented both in 0.13-μm and 65-nm (BPTM) bulk CMOS processes, the proposed method shows a high accuracy in estimating leakage power.

• Type: Conference
• Year: 2006
• Where: ISQED
• Authors: Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson
• Keywords: Hardware, ISQED 2006, Leakage Power, Leakage Power Values, Power Estimation Method