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» Strategies to Parallelize ILP Systems
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DAC
2005
ACM
13 years 10 months ago
Dynamic reconfiguration with binary translation: breaking the ILP barrier with software compatibility
In this paper we present the impact of dynamically translating any sequence of instructions into combinational logic. The proposed approach combines a reconfigurable architecture ...
Antonio Carlos Schneider Beck, Luigi Carro
RTCSA
2006
IEEE
14 years 2 months ago
Instruction Scheduling with Release Times and Deadlines on ILP Processors
ILP (Instruction Level Parallelism) processors are being increasingly used in embedded systems. In embedded systems, instructions may be subject to timing constraints. An optimisi...
Hui Wu, Joxan Jaffar, Jingling Xue
ACIVS
2005
Springer
14 years 2 months ago
Designing Area and Performance Constrained SIMD/VLIW Image Processing Architectures
Abstract. Image processing is widely used in many applications, including medical imaging, industrial manufacturing and security systems. In these applications, the size of the ima...
Hamed Fatemi, Henk Corporaal, Twan Basten, Richard...
EH
2004
IEEE
117views Hardware» more  EH 2004»
14 years 4 days ago
Multi-objective Optimization of a Parameterized VLIW Architecture
The use of Application Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...
ILP
2004
Springer
14 years 1 months ago
On the Effect of Caching in Recursive Theory Learning
This paper focuses on inductive learning of recursive logical theories from a set of examples. This is a complex task where the learning of one predicate definition should be inter...
Margherita Berardi, Antonio Varlaro, Donato Malerb...