871 search results - page 105 / 175 » Streaming Reduction Circuit |
DSN
2005
IEEE
14 years 8 days ago
2005
IEEE
The increasing transient fault rate will necessitate onchip fault tolerance techniques in future processors. The speed gap between the processor and the memory is also increasing,...
DAC
2004
ACM
14 years 11 months ago
2004
ACM
The advent of strong multi-level partitioners has made topdown min-cut placers a favored choice for modern placer implementations. We examine terminal propagation, an important st...
ICCAD
2008
IEEE
14 years 7 months ago
2008
IEEE
This paper describes an efficient implementation of an effective sequential synthesis operation that uses induction to detect and merge sequentially-equivalent nodes. State-encodi...
DAC
2009
ACM
14 years 5 months ago
2009
ACM
This paper describes an automatic methodology for optimizing sample point selection for using in the framework of model order reduction (MOR). The procedure, based on the maximiza...
GLVLSI
2006
IEEE
14 years 4 months ago
2006
IEEE
We present the design of high-performance and energy-efficient dynamic instruction schedulers in a 3-Dimensional integration technology. Based on a previous observation that the c...