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DAC
2002
ACM
14 years 10 months ago
Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique
Reducing power dissipation is one of the most principle subjects in VLSI design today. Scaling causes subthreshold leakage currents to become a large component of total power diss...
Mohab Anis, Mohamed Mahmoud, Mohamed I. Elmasry, S...
ENGL
2008
79views more  ENGL 2008»
13 years 10 months ago
Cost Reduction in Nearest Neighbour Based Synthesis of Quantum Boolean Circuits
Quantum computer algorithms require an `oracle' as an integral part. An oracle is a reversible quantum Boolean circuit, where the inputs are kept unchanged at the outputs and ...
Mozammel H. A. Khan
ISVLSI
2005
IEEE
129views VLSI» more  ISVLSI 2005»
14 years 3 months ago
Reduction of Direct Tunneling Power Dissipation during Behavioral Synthesis of Nanometer CMOS Circuits
— Direct tunneling current is the major component of static power dissipation of a CMOS circuit for technology below 65nm, where the gate dielectric (SiO2) is very low. We intuit...
Saraju P. Mohanty, Ramakrishna Velagapudi, Valmiki...
ASPDAC
1995
ACM
79views Hardware» more  ASPDAC 1995»
14 years 1 months ago
Search space reduction in high level synthesis by use of an initial circuit
Most existing high-level synthesis(HLS) systems attempt to generate a circuit from a behavioral description \out of the void", using the entire design space as the search dom...
Atsushi Masuda, Hiroshi Imai, Jeffery P. Hansen, M...
ESSCIRC
2011
93views more  ESSCIRC 2011»
12 years 9 months ago
12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 volta
— Within-functional-block fine-grained adaptive dual supply voltage control (FADVC) is proposed to reduce the power of CMOS logic circuits. Both process and design variations wi...
Atsushi Muramatsu, Tadashi Yasufuku, Masahiro Nomu...