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VLSID
2007
IEEE
131views VLSI» more  VLSID 2007»
14 years 4 months ago
A Placement Methodology for Robust Clocking
As the VLSI technology scales towards the nanometer regime, circuit performance is increasingly affected by variations. These variations need to be considered at an early stage in...
Ganesh Venkataraman, Jiang Hu
VLSI
2007
Springer
14 years 4 months ago
Incremental placement for structured ASICs using the transportation problem
— While physically driven synthesis techniques have proven to be an effective method to meet tight timing constraints required by a design, the incremental placement step during ...
Andrew C. Ling, Deshanand P. Singh, Stephen Dean B...
APCCAS
2006
IEEE
229views Hardware» more  APCCAS 2006»
14 years 4 months ago
Low Power Combinational Multipliers using Data-driven Signal Gating
— A data driven approach to design and optimization of low power combinational multipliers is presented. This technique depends on signal gating to avoid un-necessary computation...
Nima Honarmand, Ali Afzali-Kusha
ISPD
2004
ACM
92views Hardware» more  ISPD 2004»
14 years 3 months ago
A predictive distributed congestion metric and its application to technology mapping
Due to increasing design complexity, routing congestion has become a critical problem in VLSI designs. This paper introduces a distributed metric to predict routing congestion for...
Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant S...
FPL
2004
Springer
72views Hardware» more  FPL 2004»
14 years 3 months ago
Simultaneous Timing Driven Clustering and Placement for FPGAs
Traditional placement algorithms for FPGAs are normally carried out on a fixed clustering solution of a circuit. The impact of clustering on wirelength and delay of the placement s...
Gang Chen, Jason Cong