A predictive distributed congestion metric and its application to technology mapping

Due to increasing design complexity, routing congestion has become a critical problem in VLSI designs. This paper introduces a distributed metric to predict routing congestion for a premapped netlist and applies it to technology mapping that targets area optimization. Our technology mapping algorithm is guided by a probabilistic congestion map for the subject graph to identify the congested regions. Experimental results on the benchmark circuits in a 90nm technology show that congestion-aware mapping results in a reduction of 37%, on an average, in track overflows as compared to conventional technology mapping. Categories and Subject Descriptors B.6.3 [Design Aids]: Automatic syntheis; Optimization General Terms Algorithms, Design Keywords Congestion prediction, technology mapping

• Type: Conference
• Year: 2004
• Where: ISPD
• Authors: Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang
• Keywords: Hardware, ISPD 2004, Probabilistic Congestion Map, Technology Mapping, Technology Mapping Algorithm