871 search results - page 128 / 175 » Streaming Reduction Circuit |
122
click to vote
DAC
2005
ACM
15 years 4 months ago
2005
ACM
This paper presents a new test response compaction technique with any number of unknown logic values (X’s) in the test response bits. The technique leverages an X-tolerant respo...
118
click to vote
CRYPTO
2010
Springer
15 years 4 months ago
2010
Springer
The search for encryption schemes that allow to evaluate functions (or circuits) over encrypted data has attracted a lot of attention since the seminal work on this subject by Rive...
112
click to vote
VLSISP
2002
15 years 2 months ago
2002
3:2 counters and 4:2 compressors have been widely used for multiplier implementations. In this paper, a fast 5:3 compressor is derived for high-speed multiplier implementations. Th...
149
click to vote
ETS
2009
IEEE
2009
IEEE
Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques
15 years 22 days ago
Due to the increased speed in modern designs, testing for delay faults has become an important issue in the postproduction test of manufactured chips. A high fault coverage is nee...
104
click to vote
TCAD
2010
14 years 9 months ago
2010
Abstract--An efficient passivity test based on canonical projector techniques is proposed for descriptor systems (DSs) widely encountered in circuit and system modeling. The test f...