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FPGA
2003
ACM
167views FPGA» more  FPGA 2003»
15 years 12 months ago
A scalable 2 V, 20 GHz FPGA using SiGe HBT BiCMOS technology
This paper presents a new power saving, high speed FPGA design enhancing a previous SiGe CML FPGA based on the Xilinx 6200 FPGA. The design aims at having a higher performance but...
Jong-Ru Guo, Chao You, Kuan Zhou, Bryan S. Goda, R...
157
Voted
FPL
2009
Springer
86views Hardware» more  FPL 2009»
15 years 11 months ago
Improving logic density through synthesis-inspired architecture
We leverage properties of the logic synthesis netlist to define both a logic element architecture and an associated technology mapping algorithm that together provide improved lo...
Jason Helge Anderson, Qiang Wang
FOCS
1999
IEEE
15 years 11 months ago
Near-Optimal Conversion of Hardness into Pseudo-Randomness
Various efforts ([?, ?, ?]) have been made in recent years to derandomize probabilistic algorithms using the complexity theoretic assumption that there exists a problem in E = dti...
Russell Impagliazzo, Ronen Shaltiel, Avi Wigderson
JOCN
2010
71views more  JOCN 2010»
15 years 5 months ago
Mechanisms and Dynamics of Cortical Motor Inhibition in the Stop-signal Paradigm: A TMS Study
■ The ability to stop ongoing motor responses in a splitsecond is a vital element of human cognitive control and flexibility that relies in large part on prefrontal cortex. We u...
Wery P. M. van den Wildenberg, Borís Burle,...
188
Voted
TC
2010
15 years 5 months ago
Redundant-Digit Floating-Point Addition Scheme Based on a Stored Rounding Value
—Due to the widespread use and inherent complexity of floating-point addition, much effort has been devoted to its speedup via algorithmic and circuit techniques. We propose a ne...
Ghassem Jaberipur, Behrooz Parhami, Saeid Gorgin