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ICCD
2003
IEEE
89views Hardware» more  ICCD 2003»
14 years 6 months ago
Precomputation-based Guarding for Dynamic and Leakage Power Reduction
- This paper presents a precomputation-based guarding technique to reduce both dynamic and static power consumptions in CMOS VLSI circuits. More precisely, a high threshold sleep t...
Afshin Abdollahi, Massoud Pedram, Farzan Fallah, I...
ISLPED
2005
ACM
110views Hardware» more  ISLPED 2005»
14 years 3 months ago
Complexity reduction in an nRERL microprocessor
We describe an adiabatic microprocessor implemented with a reversible logic, nRERL [1]. We employed an 8-phase clocked power instead of 6-phase one to reduce the number of buffers...
Seokkee Kim, Soo-Ik Chae
TCAD
2010
164views more  TCAD 2010»
13 years 4 months ago
Advanced Variance Reduction and Sampling Techniques for Efficient Statistical Timing Analysis
The Monte-Carlo (MC) technique is a traditional solution for a reliable statistical analysis, and in contrast to probabilistic methods, it can account for any complicate model. How...
Javid Jaffari, Mohab Anis
AAAI
2007
14 years 5 days ago
Online Co-Localization in Indoor Wireless Networks by Dimension Reduction
This paper addresses the problem of recovering the locations of both mobile devices and access points from radio signals that come in a stream manner, a problem which we call onli...
Jeffrey Junfeng Pan, Qiang Yang, Sinno Jialin Pan
DAC
2005
ACM
14 years 10 months ago
A novel synthesis approach for active leakage power reduction using dynamic supply gating
: Due to exponential increase in subthreshold leakage with technology scaling and temperature increase, leakage power is becoming a major fraction of total power in the active mode...
Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hami...