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ASPDAC
2006
ACM
117views Hardware» more  ASPDAC 2006»
14 years 3 months ago
Signal-path driven partition and placement for analog circuit
This paper advances a new methodology based on signal-path information to resolve the problem of device-level placement for analog layout. This methodology is mainly based on three...
Di Long, Xianlong Hong, Sheqin Dong
ICCD
2008
IEEE
498views Hardware» more  ICCD 2008»
14 years 6 months ago
Run-time Active Leakage Reduction by power gating and reverse body biasing: An eNERGY vIEW
— Run-time Active Leakage Reduction (RALR) is a recent technique and aims at aggressively reducing leakage power consumption. This paper studies the feasibility of RALR from the ...
Hao Xu, Ranga Vemuri, Wen-Ben Jone
DATE
2000
IEEE
142views Hardware» more  DATE 2000»
14 years 2 months ago
Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...
Balakrishna Kumthekar, Fabio Somenzi
ISCAS
2005
IEEE
107views Hardware» more  ISCAS 2005»
14 years 3 months ago
Discrete and continuous substrate noise spectrum dependence on digital circuit characteristics
—This work presents an experimental investigation about the relation between specific characteristics of a digital circuit (clock frequency and architecture) and the substrate no...
Enrique Barajas, Luis Elvira, Miguel A. Mén...
ISCAS
2005
IEEE
126views Hardware» more  ISCAS 2005»
14 years 3 months ago
Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits
—Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits is presented in this paper. Noise immunity is enhanced by conditionally turning on the conditional k...
Chung-Hsien Hua, Wei Hwang, Chih-Kai Chen