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CSREAESA
2003
13 years 11 months ago
Power Optimized Combinational Logic Design
In this paper we address the problem of minimization of power consumption in combinational circuits by minimizing the number of switching transitions at the output nodes of each g...
R. V. Menon, S. Chennupati, Naveen K. Samala, Damu...
ESANN
2007
13 years 11 months ago
Kernel-based online machine learning and support vector reduction
We apply kernel-based machine learning methods to online learning situations, and look at the related requirement of reducing the complexity of the learnt classifier. Online meth...
Sumeet Agarwal, V. Vijaya Saradhi, Harish Karnick
ICCAD
2006
IEEE
107views Hardware» more  ICCAD 2006»
14 years 6 months ago
Decoupling capacitor planning and sizing for noise and leakage reduction
—Decoupling capacitors (decaps) are a popular means for reducing power-supply noise in integrated circuits. Since the decaps are usually inserted in the whitespace of the device ...
Eric Wong, Jacob R. Minz, Sung Kyu Lim
ICCAD
2006
IEEE
132views Hardware» more  ICCAD 2006»
14 years 4 months ago
Clock buffer polarity assignment for power noise reduction
Abstract—Power/ground noise is a major source of VLSI circuit timing variations. This work aims to reduce clock network induced power noise by assigning different signal polariti...
Rupak Samanta, Ganesh Venkataraman, Jiang Hu
ICIP
2002
IEEE
14 years 11 months ago
Rate-reduction transcoding design for wireless video streaming
This paper presents two types of techniques suitable for rate reduction transcoding for wireless video streaming applications. We begin this paper by reviewing existing approaches...
Anthony Vetro, Chang Wen Chen