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TIM
2010
294views Education» more  TIM 2010»
13 years 4 months ago
Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems
In this paper, a novel low-power design technique is proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating the ...
HeungJun Jeon, Yong-Bin Kim, Minsu Choi
JCSS
1998
74views more  JCSS 1998»
13 years 9 months ago
Reductions in Circuit Complexity: An Isomorphism Theorem and a Gap Theorem
We show that all sets that are complete for NP under non-uniform AC0 reductions are isomorphic under non-uniform AC0-computable isomorphisms. Furthermore, these sets remain NP-com...
Manindra Agrawal, Eric Allender, Steven Rudich
SAC
2008
ACM
13 years 9 months ago
Sensor stream reduction for clustered wireless sensor networks
This work presents the use of sensor stream reduction algorithms in clustered wireless sensor networks (WSNs), where the cluster head node is responsible to reduce the amount of d...
André L. L. de Aquino, Carlos Mauricio S. F...
ICCD
2004
IEEE
154views Hardware» more  ICCD 2004»
14 years 6 months ago
Transistor and Pin Reordering for Gate Oxide Leakage Reduction in Dual T{ox} Circuits
Gate oxide tunneling current (Igate) is emerging as a key roadblock for device scaling in nanometer-scale CMOS circuits. A practical means to reduce Igate is to leverage dual Tox ...
Anup Kumar Sultania, Dennis Sylvester, Sachin S. S...
ASPDAC
1999
ACM
144views Hardware» more  ASPDAC 1999»
14 years 2 months ago
Model Order Reduction of Large Circuits Using Balanced Truncation
A method is introduced for model order reduction of large circuits extracted from layout. The algorithm, which is based on balanced realization, can be used for reducing the order ...
Payam Rabiei, Massoud Pedram