In this paper, a novel low-power design technique is proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating the ...
We show that all sets that are complete for NP under non-uniform AC0 reductions are isomorphic under non-uniform AC0-computable isomorphisms. Furthermore, these sets remain NP-com...
This work presents the use of sensor stream reduction algorithms in clustered wireless sensor networks (WSNs), where the cluster head node is responsible to reduce the amount of d...
Gate oxide tunneling current (Igate) is emerging as a key roadblock for device scaling in nanometer-scale CMOS circuits. A practical means to reduce Igate is to leverage dual Tox ...
Anup Kumar Sultania, Dennis Sylvester, Sachin S. S...
A method is introduced for model order reduction of large circuits extracted from layout. The algorithm, which is based on balanced realization, can be used for reducing the order ...