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FPGA
1998
ACM
125views FPGA» more  FPGA 1998»
14 years 2 months ago
Timing Driven Floorplanning on Programmable Hierarchical Targets
The goal of this paper is to perform a timing optimization of a circuit described by a network of cells on a target structure whose connection delays have discrete values following...
S. A. Senouci, A. Amoura, Helena Krupnova, Gabriel...
DAC
1997
ACM
14 years 2 months ago
An Improved Algorithm for Minimum-Area Retiming
The concept of improving the timing behavior of a circuit by relocating flip-flops is called retiming and was first presented by Leiserson and Saxe. The ASTRA algorithm propose...
Naresh Maheshwari, Sachin S. Sapatnekar
ICCAD
1996
IEEE
131views Hardware» more  ICCAD 1996»
14 years 2 months ago
Multi-level logic optimization for low power using local logic transformations
In this paper we present an ecient technique to reduce the switching activity in a CMOS combinational logic network based on local logic transformations. These transformations con...
Qi Wang, Sarma B. K. Vrudhula
DSD
2004
IEEE
169views Hardware» more  DSD 2004»
14 years 2 months ago
Shift Invert Coding (SINV) for Low Power VLSI
Low power VLSI circuit design is one of the most important issues in present day technology. One of the ways of reducing power in a CMOS circuit is to reduce the number of transit...
Jayapreetha Natesan, Damu Radhakrishnan
TCAD
2002
128views more  TCAD 2002»
13 years 10 months ago
Preferred direction Steiner trees
Interconnect optimization for VLSI circuits has received wide attention. To model routing surfaces, multiple circuit layers are freabstracted as a single rectilinear plane, ignori...
Mehmet Can Yildiz, Patrick H. Madden