871 search results - page 9 / 175 » Streaming Reduction Circuit |
IPPS
2005
IEEE
14 years 3 months ago
2005
IEEE
The use of pipelined floating-point arithmetic cores to create high-performance FPGA-based computational kernels has introduced a new class of problems that do not exist when usi...
DAC
2007
ACM
14 years 1 months ago
2007
ACM
RLC circuits have been shown to be better formulated as second-order systems instead of first-order systems. The corresponding model order reduction techniques for secondorder sys...
JSA
2006
13 years 9 months ago
2006
A NULL Cycle Reduction (NCR) technique is developed to increase the throughput of NULL Convention Logic systems, by reducing the time required to flush complete DATA wavefronts, c...
DATE
2007
IEEE
14 years 4 months ago
2007
IEEE
In this paper, we propose a novel statistical model order reduction technique, called statistical spectrum model order reduction (SSMOR) method, which considers both intra-die and...
DAC
1999
ACM
14 years 2 months ago
1999
ACM
ENOR is an innovative way to produce provablypassive, reciprocal, and compact representations of RLC circuits. Beginning with the nodal equations, ENOR formulates recurrence relat...